Semiconductor device and method of manufacturing same

ABSTRACT

To provide a semiconductor device having improved reliability. The semiconductor device is equipped with a first polyimide film, rewirings formed over the first polyimide film, first and second dummy patterns formed over the first polyimide film, a second polyimide film that covers the rewirings and the dummy patterns, and an opening portion that exposes a portion of the rewirings in the second polyimide film. The first dummy pattern is, in plan view, comprised of a closed pattern surrounding the rewirings while having a space therebetween.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation application of U.S. application Ser.No. 15/231,820, filed Aug. 9, 2016, the disclosure of Japanese PatentApplication No. 2015-167283 filed on Aug. 26, 2015 including thespecification, drawings, and abstract is incorporated herein byreference in its entirety.

BACKGROUND

The present invention relates to a semiconductor device and itsmanufacturing technology, for example, a semiconductor device having arewiring (redistribution layer) and a technology effective when it isapplied to the manufacturing technology of the semiconductor device.

Japanese Unexamined Patent Application Publication No. 2014-22505(Patent Document 1) describes a structure in which a rewiring iscomprised of a copper film (Cu film), a nickel film (Ni film), and apalladium film (Pd film) successively stacked from the side of asemiconductor substrate and a copper wire is coupled to the uppersurface of the palladium film.

Japanese Patent No. 5412552 (Patent Document 2) describes that apredetermined or more occupancy of a rewiring is required for stableformation of a copper film by plating.

Japanese Patent No. 5132162 (Patent Document 3) describes arrangement ofa dummy pattern at the side of a fuse wiring as an arrangement exampleof a dummy pattern around a wiring.

Japanese Unexamined Patent Application Publication No. 2012-253071(Patent Document 4) describes a technology of placing a dummy patterncomprised of a dot pattern around a wiring layer.

Japanese Unexamined Patent Application Publication No. Hei5(1993)-258017 (Patent Document 5) describes a technology of arrangingdummy patterns in mesh form at the entire periphery except wirings.

PATENT DOCUMENT

[Patent Document 1] Japanese Unexamined Patent Application PublicationNo. 2014-22505

[Patent Document 2] Japanese Patent No. 5412552

[Patent Document 3] Japanese Patent No. 5132162

[Patent Document 4] Japanese Unexamined Patent Application PublicationNo. 2012-253071

[Patent Document 5] Japanese Unexamined Patent Application PublicationNo. Hei 5(1993)-258017

SUMMARY

Development trends of semiconductor devices to be used for, for example,consumer products typified by household electric appliances orcommunication equipment are to reduce power consumption, downsize thedevice, and reduce a production cost. Semiconductor devices forvehicles, on the other hand, need improvement in reliability ofhigh-voltage operation under high-temperature environments in additionto the above-described development trends. In order to meet thesetrends, using an inexpensive copper (Cu) wire instead of an expensivegold (Au) wire have been investigated from the standpoint of promotingcost reduction. In this case, however, a copper wire harder than a goldwire is likely to damage a pad to which the wire is coupled. When acopper wire is used, therefore, not coupling the copper wire directly toa pad but formation of a rewiring made of a copper wiring to be coupledto a pad and coupling this rewiring to the copper wire is underinvestigation. This rewiring structure enables reduction in ONresistance of a power transistor due to the use of a thick-film rewiringor reduction in chip area attributable to a wiring layout design usingthe rewiring. Further, cost reduction can be achieved by using acoupling structure to an inexpensive copper wire and at the same time,improvement in radiation property can be achieved by increasing an areaoccupied by a rewiring.

In such a rewiring structure, due to low adhesion between a rewiringcomposed mainly of a copper film and a copper wire, a bonding film isformed on the surface of the rewiring in order to improve adhesion withthe copper wire. As a result of investigation, however, the presentinventors have found newly that corrosion of the rewiring (copper film)occurs due to peeling of the bonding film. According to theinvestigation by the present inventors, therefore, there is room ofimprovement in the conventionally used rewiring structure from thestandpoint of reliability of a semiconductor device.

Another problem and novel features of the invention will be apparentfrom the description herein and accompanying drawings.

In a semiconductor device according to one embodiment, a conductorpattern is arranged so as to surround, in plan view, a rewiring, whilehaving a space therebetween and this conductor pattern is comprised of aclosed pattern.

According to the one embodiment, a semiconductor device having improvedreliability can be provided.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified cross-sectional view showing a manufacturing stepof a rewiring structure in the related art;

FIG. 2 is another simplified cross-sectional view showing amanufacturing step of the rewiring structure in the related art;

FIG. 3 is a further simplified cross-sectional view showing amanufacturing step of the rewiring structure in the related art;

FIG. 4 schematically shows, when a copper film has an inverted taperedside surface, formation of a stacked film of a titanium film and apalladium film and a titanium film by sputtering so as to cover thesurface and the side surface of the copper film;

FIG. 5A is a cross-sectional view showing two adjacent copper filmsformed using a patterned resist film and FIG. 5B is a cross-sectionalview after removal of the resist film after the step FIG. 5A;

FIG. 6A is a cross-sectional view showing two adjacent copper filmsformed using a patterned resist film and FIG. 6B is a cross-sectionalview after removal of the resist film after the step of FIG. 6A;

FIG. 7A shows a planar configuration of a semiconductor wafer and FIG.7B is an enlarged schematic view of its chip region;

FIG. 8 is a schematic view showing the configuration of a controlstrategy;

FIG. 9 shows the layout configuration of a semiconductor chip in FirstEmbodiment;

FIG. 10 is a cross-sectional view taken along the line A-A of FIG. 9;

FIG. 11 is a cross-sectional view showing a manufacturing step of asemiconductor device of First Embodiment;

FIG. 12 is a cross-sectional view showing a manufacturing step of thesemiconductor device following that of FIG. 11;

FIG. 13 is a cross-sectional view showing a manufacturing step of thesemiconductor device following that of FIG. 12;

FIG. 14 is a cross-sectional view showing a manufacturing step of thesemiconductor device following that of FIG. 13;

FIG. 15 is a cross-sectional view showing a manufacturing step of thesemiconductor device following that of FIG. 14;

FIG. 16 is a cross-sectional view showing a manufacturing step of thesemiconductor device following that of FIG. 15;

FIG. 17 is a cross-sectional view showing a manufacturing step of thesemiconductor device following that of FIG. 16;

FIG. 18 is a cross-sectional view showing a manufacturing step of thesemiconductor device following that of FIG. 17;

FIG. 19 is a cross-sectional view showing a manufacturing step of thesemiconductor device following that of FIG. 18;

FIG. 20 is a cross-sectional view showing a manufacturing step of thesemiconductor device following that of FIG. 19;

FIG. 21 is a cross-sectional view showing a manufacturing step of thesemiconductor device following that of FIG. 20;

FIG. 22 is a cross-sectional view showing a manufacturing step of thesemiconductor device following that of FIG. 21;

FIG. 23 shows one example of a hardware configuration of a layout datacreation apparatus in First Embodiment;

FIG. 24 shows a functional block configuration of the layout datacreation apparatus in First Embodiment;

FIG. 25 is a flow chart showing the flow of a layout data creationmethod in First Embodiment;

FIG. 26 is a schematic view showing a wiring pattern;

FIG. 27 is a schematic view showing a first pattern;

FIG. 28 is a schematic view showing a second pattern;

FIG. 29 is a schematic view showing a dummy pattern;

FIG. 30 is a schematic view showing a layout pattern;

FIG. 31A and FIG. 31B are schematic views describing the details offirst correction processing at a layout data creation unit;

FIG. 32A and FIG. 32B are schematic views describing the details ofsecond correction processing at a layout data creation unit;

FIG. 33 shows a layout configuration of a semiconductor chip in SecondEmbodiment;

FIG. 34 shows a layout configuration of a semiconductor chip in ThirdEmbodiment;

FIG. 35 shows another layout configuration of a semiconductor chip inThird Embodiment; and

FIG. 36 shows a layout configuration of a semiconductor chip inModification Example.

DETAILED DESCRIPTION

In the following embodiments, a description will be made after dividedinto a plurality of sections or embodiments if necessary for the sake ofconvenience. These sections or embodiments are not independent from eachother unless otherwise particularly specified, but one of them may be amodification example, details, complementary description, or the like ofa part or whole of the other one.

In the following embodiments, when a reference is made to the number(including the number, value, amount, range, or the like) of acomponent, the number is not limited to a specific number but may bemore or less than the specific number, unless otherwise particularlyspecified or principally apparent that the number is limited to thespecific number.

Further, it is needless to say that in the following embodiments, theconstituent component (including component step or the like) is notalways essential unless otherwise particularly specified or principallyapparent that it is essential.

Similarly, in the following embodiments, when a reference is made to theshape, positional relationship, or the like of the constituentcomponent, that substantially approximate or analogous to its shape orthe like is also embraced unless otherwise particularly specified orprincipally apparent that it is not. This also applies to theabove-described number and range.

In all the drawings for describing the embodiment, the same members willbe identified by the same reference numerals in principle andoverlapping descriptions will be omitted. To facilitate understandingthe drawings, even plan views are sometimes hatched.

First Embodiment <Investigation of Improvement>

Room for improvement found, in the related art, newly by the presentinventors will be described first while referring to drawings. The term“related art” as used herein means a technology having a problem foundnewly by the present inventors and is not a known conventionaltechnology. It is a technology described as a premise technology(unknown technology) of a novel technical concept.

FIGS. 1 to 3 are simplified cross-sectional views of a manufacturingstep of a rewiring structure in the related art. In FIG. 1, aninterlayer insulating film IL has thereon a pad PD and the interlayerinsulating fil IL covering the pad PD has thereon a surface protectionfilm (passivation film) PAS made of, for example, a silicon oxide filmor a silicon nitride film. This surface protection film PAS has thereinan opening portion OP1 and from this opening portion OP1, the surface ofthe pad PD is partially exposed. The surface protection film PAS havingtherein the opening portion OP1 has thereon a polyimide film PIF1 andthis polyimide film PIF1 has therein an opening portion OP2 whichcouples with the opening portion OP1. The polyimide film PIF1 includingthe inner wall of the opening portion OP1 and the inner wall of theopening portion OP2 has thereon a barrier conductor film BCF made of,for example, a titanium film or a titanium nitride film. This barrierconductor film BCF has thereon a seed film SDF made of a copper film.This seed film SDF has thereon a resist film PR1 and this resist filmPR1 is a patterned one. More specifically, the patterning of the resistfilm PR1 has been performed so as to form therein an opening portionOP(L) for forming a wiring, forming a rewiring. Manufacturing steps ofthe above-described structure are omitted, but the structure shown inFIG. 1 is formed by these omitted steps.

It is necessary that in this structure, the rewiring formed is as thickas, for example, about 10 μm and the opening portion OP(L) for formingthe wiring has a depth equal to or greater than the thickness of therewiring. The resist film PR1 is therefore required to be as thick asabout 15 μm. The resist film PR1 is patterned typically by exposuretreatment but when the resist film PR1 is thick, the resist film PR1after patterning cannot always have a stable shape by exposure treatmentonly. With a view to forming a stable pattern shape, the resist film PR1subjected to exposure treatment is then subjected to, for example,curing treatment for curing the resist film PR1 by exposure toultraviolet rays. Curing the resist film PR1 enables the patternedresist film to have a more stable shape.

When the resist film PR1 is subjected to curing treatment, however,shrinkage of the resist film PR1 occurs. Particularly in the surface ofthe resist film PR1 directly exposed to ultraviolet rays, the shrinkageof the resist film PR1 becomes marked. Curing treatment of the patternedresist film PR1 therefore increases shrinkage of the surface of theresist film PR1. This results in inclination, into a tapered shape, ofthe side surface of the opening portion OP(L) for forming the wiring asshown in FIG. 2.

When in such a state, a copper film CUF is caused to grow on the seedfilm SDF exposed from the opening portion OP(L) for forming the wiringby electroplating as shown in FIG. 3, the side surface of the copperfilm CUF inevitably has an inverted tapered shape because the openingportion OP(L) for forming the wiring has a tapered side surface. Thepresent inventors have thus found newly that the side surface of thecopper film CUF formed by electroplating has an inverted tapered shapewhen the resist film PR1 is subjected to curing treatment.

In the above-described structure, the rewiring comprised mainly of thecopper film CUF is coupled to a copper wire. Since adhesion between thecopper film CUF and the copper wire is not good, it is the commonpractice not to directly couple the copper film CUF to the copper wirebut insert a bonding film between the copper film CUF and the copperwire. Described specifically, it is the common practice to form astacked film of a nickel film and a gold film in a partial region of thesurface of the copper film CUF and couple the copper film CUF to thecopper wire via the stacked film. In this case, the copper wire isdirectly coupled to the gold film superior in adhesion so that thecoupling reliability between the rewiring and the copper wire can beimproved. In this configuration, the nickel film and the gold film areformed typically by plating. Even when the copper film CUF has aninverted tapered side surface, deterioration in the reliability of therewiring due to the inverted tapered shape does not become apparent.

However, it has recently been investigated to use, as the bonding film,a stacked film of a titanium film (Ti film) and a palladium film (Pdfilm) superior in adhesion with the copper film CUF, instead of anexpensive gold film, in order to reduce a manufacturing cost of asemiconductor device. Further, when the stacked film of a titanium filmand a palladium film is used as the bonding film because of a cost lowerthan that of the gold film, not only a portion of the surface of thecopper film CUF but also the surface and side surface of the copper filmCUF may be covered with it. In short, using the stacked film of atitanium film and a palladium film is advantageous that not only itimproves adhesion between the copper film CUF and the copper wire butalso it adds another function of protecting the copper film CUF fromcorrosion or the like. When the gold film is used as the bonding film,the gold film is formed only in a bonding region to the copper wire inorder to suppress a using amount of such an expensive gold film to theminimum. On the other hand, the stacked film of a titanium film and apalladium film can be formed so as to cover not only the bonding regionto the copper wire but also the surface and the side surface of thecopper film CUF because it needs a cost lower than that of the goldfilm. In short, using, as the bonding film, the stacked film of atitanium film and a palladium film therefore contributes to costreduction of a semiconductor device and also to protection of the copperfilm CUF from corrosion or the like. As a result, a semiconductor devicehaving improved reliability can be provided.

The present inventors have found newly that when the stacked film of atitanium film and a palladium film is used as the bonding film, however,room for improvement becomes apparent because the copper film CUF has aninverted tapered side surface. Described specifically, in order to coverthe surface and side surface of the copper film CUF with the stackedfilm of a titanium film and a palladium film, for example, sputtering isused. Since the copper film CUF formed by sputtering has an invertedtapered side surface, room for improvement becomes apparent. Adescription will next be made on this point.

FIG. 4 schematically shows formation of a stacked film PDF of a titaniumfilm and a palladium film and a titanium film TF by sputtering so as tocover the surface and side surface of the copper film CUF when thecopper film CUF has an inverted tapered side surface. Since sputteringshown by the arrows in FIG. 4 has directivity, the thickness of thestacked film PDF and that of the titanium film TF in a region A1 in thevicinity of the side surface of the copper film CUF become thinner thanthose in the other region. In other words, when the copper film CUF hasan inverted tapered side surface, film forming particles do not adherewell to the side surface of the copper film CUF, leading to thinning ofthe stacked film PDF and the titanium film TF. Patterning of thetitanium film TF or the stacked film PDF by wet etching under such astate is likely to cause peeling of the titanium film TF or the stackedfilm PDF in the region A1 in the vicinity of the side surface of thecopper film CUF. This film peeling then causes corrosion of the copperfilm CUF. In addition, foreign matters are produced by this filmpeeling. Thus, when the copper film CUF has an inverted tapered sidesurface, the semiconductor device thus manufactured may inevitably havedeteriorated reliability or a yield in the manufacturing steps of thesemiconductor device may be reduced.

Thus, when the copper film CUF has an inverted tapered side surface,even covering of the surface and side surface of the copper film CUF bythe stacked film PDF of a titanium film and a palladium film to protectthem with the stacked film results in failure because, due to thinningof the stacked film PDF on the side surface of the copper film CUF, filmpeeling or generation of foreign matters occurs, which becomes apparentas room for improvement. In particular, this room for improvementbecomes apparent when the stacked film PDF is formed by sputtering.

In First Embodiment, a measure is taken to overcome the above-describedproblem of the related art to be improved. The technical concept ofFirst Embodiment taking this measure will hereinafter be described.First, a description will be made on the finding of the presentinventors. Then, a control strategy for actualizing this finding will bedescribed and then, another problem which will appear in this controlstrategy will next be described. The technical concept of FirstEmbodiment then follows.

<Finding by the Present Inventors>

The finding by the present inventors will be described referring to somedrawings. FIGS. 5 show formation of two adjacent copper films CUF1 andCUF2 by using a patterned resist film PR1. In particular, FIGS. 5 show aschematic view showing a configuration in which a distance between thecopper film CUF1 and the copper film CUF2 is large and therefore, thewidth of the resist film PR1 sandwiched between the copper film CUF1 andthe copper film CUF2 becomes large. FIG. 5A is a cross-sectional viewshowing the copper film CUF1 and the copper film CUF2 formed using apatterned resist film PR1, while FIG. 5B is a cross-sectional view afterremoval of the resist film PR1 after the step of FIG. 5A. First, in FIG.5A, the patterned resist film PR1 is subjected to curing treatment byexposure to ultraviolet rays and then, shrinkage of the resist film PR1occurs. In particular, as shown in FIG. 5A, as the width of the resistfilm PR1 sandwiched between the copper film CUF1 and the copper filmCUF2 becomes large, an absolute amount of shrinkage at the surface(upper surface) of the resist film PR1 becomes large. An increase in theshrinkage at the surface of the resist film PR1 means an increase in thetaper degree of the resist film PR1. In this case, therefore, as shownin FIG. 5B, the removal of the patterned resist film PR1 greatlyincreases the inverted taper degree of the side surface of the copperfilm CUF1 and at the same time, greatly increases the inverted taperdegree of the side surface of the copper film CUF2. This means that withan increase in the width of the resist fil PR1 sandwiched between thecopper film CUF1 and the copper film CUF2, the inverted taper degree ofthe copper film CUF1 and the copper film CUF2 increases greatly. Forexample, it has been verified as a result of the research by the presentinventors that when the space between the copper film CUF1 and thecopper film CUF2 is about 260 μm (the width of the resist film PR1sandwiched between the copper film CUF1 and the copper film CUF2 isabout 260 μm), the upper portion of the copper film CUF1 (copper filmCUF2) protrudes outward by about 1.2 μm, on one side, from the lowerportion.

On the other hand, FIG. 6 are each a schematic view showing aconfiguration in which a distance between the copper film CUF1 and thecopper film CUF2 is small and therefore, the width of the resist filmPR1 sandwiched between the copper film CUF1 and the copper film CUF2decreases. FIG. 6A is a cross-sectional view of the copper film CUF1 andthe copper film CUF2 formed using the patterned resist film PR1, whileFIG. 6B is a cross-sectional view showing after removal of the resistfilm PR1 after the step of FIG. 6A.

As shown in FIG. 6A, with a decrease in the width of the resist film PR1sandwiched between the copper film CUF1 and the copper film CUF2, anabsolute amount of shrinkage at the surface (upper surface) of theresist film PR1 decreases. In this case, as shown in FIG. 6B, aninverted taper degree of the side surface of the copper film CUF1 issuppressed and also an inverted taper degree of the side surface of thecopper film CUF2 is suppressed. This means that with a decrease in thewidth of the resist film PR1 sandwiched between the copper film CUF1 andthe copper film CUF2, an inverted taper degree of the copper film CUF1and the copper film CUF2 is suppressed. According to the novel findingby the present inventors, with a decrease in the width of the resistfilm PR1 sandwiched between the copper film CUF1 and the copper filmCUF2, an inverted taper degree of the copper film CUF1 and the copperfilm CUF2 is suppressed.

<Control Strategy>

Here, a control strategy for actualizing the above-described findingwill be described. FIG. 7A shows a planar configuration of asemiconductor wafer WF. As shown in FIG. 7A, the semiconductor wafer WFhas a substantially disc-shaped planar shape and it has inside thereof aplurality of chip regions CR. These chip regions CR will be individualsemiconductor chips by dicing the semiconductor wafer WF.

Next, FIG. 7B is an enlarged schematic view of the chip region CR. Asshown in FIG. 7B, the chip region CR has a rectangular shape and it has,in the inner surface region thereof, rewirings RDL. In FIG. 7B, adistance (space) between the wirings RDL is wide, meaning that theshrinkage of a resist film used for the formation of the rewiring RDLbecomes large and the resist film sandwiched between the rewirings RDLhas a tapered side surface. In this case, the rewiring RDL has aninverted tapered surface and the bonding film at the side surface of therewiring RDL becomes thin. This may lead to peeling of the bonding filmor generation of foreign matters due to this film peeling. Thesemiconductor device may presumably have deteriorated reliability or bemanufactured at a reduced manufacturing yield.

In this point, according to the control strategy, a configuration shownbelow is actualized based on a concept of minimizing the width of theresist film sandwiched between the rewirings RDL. Specifically, FIG. 8is a schematic view showing the configuration of the control strategy.As shown in FIG. 8, in the control strategy, the configuration intendedto increase the width of the rewirings RDL formed in a surface region ofthe chip region CR is actualized. According to the configuration of thiscontrol strategy, a space sandwiched between the rewirings RDL can benarrowed. This means that in the control strategy, the width of theresist film sandwiched between the rewirings RDL can be reduced when therewirings RDL are formed. According to the control strategy, therefore,an inverted tapered degree of the rewirings RDL can be suppressed.

Although the inverted taper degree of the rewirings RDL can besuppressed in the configuration according to the control strategy,another room for improvement becomes apparent. Next, the another roomfor improvement will be described.

As shown in FIG. 8, according to the control strategy, the distancebetween the rewirings RDL is reduced by increasing the width of therewirings RDL. This means a marked increase in an area occupied by therewirings RDL in the chip region CR. This causes the followinginconvenience. In the semiconductor wafer WF shown in FIG. 7A, beforethe dicing step to divide the chip region CR into individual chips, theback surface of the semiconductor wafer WF is ground to thin thesemiconductor wafer WF. As shown in FIG. 8, when the area occupied bythe rewirings RDL at the surface of each of the chip regions CR islarge, the semiconductor wafer WF warps due to a difference in linearexpansion coefficient between silicon, a main component of thesemiconductor wafer WF, and copper, a main constituent material of therewirings RDL. Such a warp may interfere with fabrication stepsthereafter including the dicing step. In the control strategy,therefore, the inverted taper degree can be suppressed, while new roomfor improvement, that is, warp of the semiconductor wafer due to anincrease in the area of the chip region CR occupied by the rewirings RDLbecomes apparent. This has revealed that the control strategy is notsufficient resolution because it causes another side effect, that is,warp of the semiconductor wafer WF. Next, the technical concept of FirstEmbodiment will therefore be described.

<Planar Layout Configuration of Semiconductor Chip in First Embodiment>

First, the planar layout configuration of a semiconductor chip in FirstEmbodiment will be described. FIG. 9 shows the planar layoutconfiguration of a semiconductor chip CHP in First Embodiment. As shownin FIG. 9, the semiconductor chip CHP in First Embodiment has, in planview, a rectangular shape. The semiconductor chip CHP has, on thesurface thereof, a rewiring RDL1 and the rewiring RDL1 is, in plan view,surrounded by a dummy pattern DP1. As shown in FIG. 9, the dummy patternDP1 is comprised of a closed pattern surrounding, in plan view, therewiring RDL1 while having a space SP1 therebetween.

Similarly, the semiconductor chip CHP has, on the surface thereof,rewirings RDL2A, RDL2B, and RDL2C and in plan view, a dummy pattern DP2surrounds these rewirings RDL2A, RDL2B, and RDL2C. At this time, asshown in FIG. 9, the dummy pattern DP2 is comprised of a closed patternsurrounding the rewirings RDL2A, RDL2B, and RDL2C, while having a spaceSP1 therebetween.

With respect to the rewiring RDL1 and the dummy pattern DP1, therewiring RDL1 and the dummy pattern DP1 have therebetween asubstantially fixed distance. In other words, the space SP1 insertedbetween the rewiring RDL1 and the dummy pattern DP1 is substantiallyfixed. Similarly, for example, with respect to the rewirings RDL2A,RDL2B, and RDL2C and the dummy pattern DP2, the space SP1 insertedbetween the rewirings RDL2A, RDL2B, and RDL2C and the dummy pattern DP2is substantially fixed. In particular, the dummy pattern DP2 iscomprised of a closed pattern surrounding a plurality of rewirings (therewirings RDL2A, RDL2B, and RDL2C). In this case, there is the space SP1between the dummy pattern DP2 and the rewirings RDL2A, RDL2B, and RDL2Cand at the same time, as shown for example in a region A3 of FIG. 9,there is a space SP2 between the rewiring RDL2A and the rewiring RDL2B.In First Embodiment, the space SP1 and the space SP2 are roughly equalto each other.

Further, as shown in a region A2 of FIG. 9, the dummy pattern DP1 andthe dummy pattern DP2 are coupled to each other and the width of acoupled portion of the dummy pattern DP1 and the dummy pattern DP2 isgreater than the width of the other portion of the dummy pattern DP1 andthe width of the other portion of the dummy pattern DP2.

The dummy pattern DP1 and the dummy pattern DP2 having such aconfiguration are patterns not functioning as a wiring and, for example,the potential of the dummy pattern DP1 and the potential of the dummypattern DP2 are a floating potential.

<Cross-Sectional Configuration of Semiconductor Chip in FirstEmbodiment>

FIG. 10 is a cross-sectional view taken along the line A-A of FIG. 9. InFIG. 10, the semiconductor chip CHP in First Embodiment has asemiconductor substrate 1S made of, for example, silicon and thesemiconductor substrate 1S has, in the surface thereof, an elementisolation region STI. An active region partitioned by the elementisolation region STI has thereon a field effect transistor Q and acapacitive element PIP. The element isolation region STI has thereon aresistive element R. The surface of the semiconductor substrate 1Shaving thereon the field effect transistor Q, capacitive element PIP,and the resistive element R is covered with a contact interlayerinsulating film CIL made of, for example, a silicon oxide film. Thiscontact interlayer insulating film CIL has therein a plug PLG thatpenetrates through the contact interlayer insulating film CIL. This plugPLG is formed by filling, for example, a contact hole with a barrierconductor film and a tungsten film.

The contact interlayer insulating film CIL having a plug PL therein hasthereon an interlayer insulating film IL1 made of, for example, asilicon oxide film or a low dielectric constant film having a dielectricconstant lower than that of a silicon oxide film. The interlayerinsulating film IL1 has therein a wiring trench and this wiring trenchis filled with a wiring WL1 comprised of, for example, a copper wiring.

Next, as shown in FIG. 10, the interlayer insulating film IL1 havingtherein the wiring WL1 has thereon an interlayer insulating film IL madeof, for example, a silicon oxide film or a low dielectric constant film.This interlayer insulating film IL has thereon a pad PD. This pad PD iscomprised of, for example, an aluminum film (Al film) or an aluminumalloy film (AlSi film, AlSiCu film, or the like). The semiconductor chipCHP in First Embodiment has a rewiring structure above the pad PD. Therewiring structure will next be described referring to FIG. 10.

In FIG. 10, the pad PD is covered with a surface protection film(passivation film) PAS made of, for example, a silicon oxide film or asilicon nitride film and this surface protection film PAS has therein anopening portion OP1 from which a portion of the surface of the pad PD isexposed. The surface protection film PAS having therein the openingportion OP1 has thereon a polyimide film PIF1 and this polyimide filmPIF1 has therein an opening portion OP2 which couples with the openingportion OP1. A rewiring RDL1 fills the opening portion OP1 and theopening portion OP2 and is allocated on the polyimide film PIF1. Therewiring RDL1 is comprised of, for example, a barrier conductor film BCFmade of a titanium film or a titanium nitride film, a copper film CUFformed on the barrier conductor film BCF, and a stacked film PDFcovering the surface and the side surface of the copper film CUF. Inparticular, the stacked film PDF is made of, for example, a titaniumfilm and a palladium film formed thereon.

The polyimide film PIF1 has thereon the dummy pattern DP1 adjacent tothe rewiring RDL1. This means that the polyimide film PIF1 has thereonthe rewiring RDL1 and the dummy pattern DP1 adjacent to each other andthe rewiring RDL1 and the dummy pattern DP1 are placed in the samelayer. The dummy pattern DP1 is also comprised of a barrier conductorfilm BCF, a copper film CUF formed on the barrier conductor film BCF,and a stacked film (Ti/Pd film) PDF that covers the surface and the sidesurface of the copper film CUF. The dummy pattern DP1 can therefore becalled a conductor pattern.

The rewiring RDL1 and the dummy pattern DP1 placed adjacent to eachother are covered by a polyimide film PIF2. This polyimide film PIF2 hastherein an opening portion OP3 that exposes a portion of the rewiringRDL1. More specifically, as shown in FIG. 10, the stacked film (Ti/Pdfilm) PDF formed on the surface of the rewiring RDL1 is exposed from theopening portion OP3 formed in the polyimide film PIF2 and a wire W madeof copper is coupled to the stacked film (Ti/Pd film) PDF exposed fromthe opening portion OP3.

The barrier conductor film BCF has a function of suppressing diffusionof copper configuring the copper film CUF. The stacked film (Ti/Pd film)PDF functions as a bonding film for improving adhesion between therewiring RDL1 and the wire W made of copper.

Characteristic of First Embodiment

The semiconductor chip CHP in First Embodiment has a configuration asdescribed above. The characteristics of the present embodiment will nextbe described. First Embodiment is characterized in that, for example, asshown in FIG. 9, the dummy pattern DP1 is provided so as to surround theperiphery of the rewiring RDL1, while having the space SP1 therebetween.In other words, the characteristic of First Embodiment is that the dummypattern DP1 is provided which is comprised of a closed patternsurrounding, in plan view, the rewiring RDL1, while having the space SP1therebetween. When the rewiring RDL1 is formed, the dummy pattern DP1surrounding the rewiring RDL1 is formed together. This means thatsimultaneously with an opening portion for forming the wiring, formingthe rewiring RDL1 in the resist film, an opening portion for forming adummy pattern, forming the dummy pattern DP1 is formed in the vicinityof the opening portion for forming the wiring. Due to the characteristicof First Embodiment, therefore, the width of the resist film presentbetween the opening portion for forming the wiring and the openingportion for forming the dummy pattern can be reduced. As a result, FirstEmbodiment enables reduction in an absolute amount of shrinkage at thesurface of the resist film, which is sandwiched between the rewiringRDL1 and the dummy pattern DP1, by curing treatment. In other words,according to the characteristic of First Embodiment, the tapered shapeof the opening portion for forming the wiring, formed in the resist filmcan be relaxed to suppress the rewiring RDL1 from having an invertedtapered side surface. According to the characteristic of FirstEmbodiment, therefore, thinning of the bonding film at the side surfaceof the rewiring RDL1, which results from that the rewiring RDL1 has aninverted tapered side surface, can be suppressed. According to FirstEmbodiment, peeling of the bonding film or generation of foreign mattersdue to this film peeling can be suppressed and as a result, thesemiconductor device thus obtained can have improved reliability and itcan be manufactured at an improved yield.

In particular, according to the characteristic of First Embodiment, aconcept of reducing the width of the resist film, which has beendescribed in the finding by the present inventors (refer to FIG. 6), isrealized not by reducing the distance between two adjacent rewirings butby forming the closed dummy pattern DP1 that surrounds the rewiring RDL1while having the space SP1 therebetween.

For example, as shown in FIG. 6, when the concept of reducing the widthof a resist film sandwiched between two adjacent rewirings is realizedby the configuration for reducing a distance between two adjacentrewirings, a drastic change in the layout of the rewiring is requiredand at the same time, excessive limitation is imposed on the layout ofthe rewiring in order to reduce the distance between two adjacentrewirings. Further, as in the control strategy shown in FIG. 8, an areaoccupied by the rewiring becomes markedly large and warp of thesemiconductor wafer appears as a problem. When the concept of reducingthe width of a resist film sandwiched between two adjacent rewirings isrealized by the configuration for reducing a distance between twoadjacent rewirings, it is accompanied with a drastic design change ofthe layout of the rewiring, excessive limitation in layout design, andmoreover, a side effect such as warp of a semiconductor wafer ascompensation for suppression of the inverted taper degree of therewiring RDL1.

On the other hand, in the configuration as described in thecharacteristic of First Embodiment in which the width of the resist filmsandwiched between the rewiring RDL1 and the dummy pattern DP1 isreduced by forming the closed dummy pattern DP1 surrounding the rewiringRDL1 while having the space SP1 therebetween, the rewiring RDL1 can besuppressed from having an inverted tapered shape without drastic designchange in the layout of the rewiring or excessive limitation in thelayout design. Further, according to the characteristic of FirstEmbodiment, a remarkable increase in the area occupied by the rewiringRDL1 as in the control strategy shown in FIG. 8 can be prevented so thatthe warp of the semiconductor wafer does not appear as a problem. Inshort, when the finding by the present inventors is realized based onthe characteristic of First Embodiment, the inverted taper degree of therewiring RDL1 can be suppressed without causing a side effect so that itis a highly useful technical concept.

Further, in First Embodiment, the space SP1 between the rewiring RDL1and the dummy pattern DP1 is substantially fixed throughout the rewiringRDL1 so that the resist film sandwiched between the rewiring RDL1 andthe dummy pattern DP1 can have a uniform width throughout the rewiringRDL1. This means that the rewiring RDL1 can be suppressed from having aninverted tapered shape uniformly all over the rewiring RDL1. In otherwords, it is possible to suppress a portion of the rewiring RDL1 fromhaving an inverted tapered shape and thereby suppress thinning of abonding film which will otherwise occur when the rewiring RDL1 has aninverted tapered side surface all over the rewiring RDL1.

The First Embodiment is also characterized in that for example, as shownin FIG. 9, the dummy pattern DP2 surrounds, via the space SP1, theperiphery of the entirety of a rewiring group comprised of the rewiringRDL2A, RDL2B, and RDL2C. This means that another characteristic of FirstEmbodiment is that the dummy pattern DP2 comprised of a closed patternthat surrounds, in plan view, the entirety of the rewiring group(rewirings RDL2A, RDL2B, and RDL2C) via the space SP1 is provided.Essentially, according to the characteristic of First Embodiment, it isassumed that one dummy pattern DP1 surrounds the periphery of onerewiring RDL1 via the space SP1. There is however a case where, forexample as shown in the region A3 of FIG. 9, a distance between therewiring RDL2A and the rewiring RDL2B is narrow and the dummy patternDP1 is hardly be placed in this narrow region via the space SP1. Toovercome such a case, providing the dummy pattern DP2 via the space SP1so as to surround the periphery of the entirety of the rewiring groupcomprised of the rewirings RDL2A, RDL2B, and RDL2C as shown in FIG. 9 isconsidered. As a result, according to First Embodiment, even when it isdifficult to provide one dummy pattern DP1 via the space SP1 so as tosurround the periphery of one rewiring RDL1, the dummy pattern DP2 canbe placed via the space SP1 for the entirety of the rewiring groupcomprised of the rewirings RDL2A, RDL2B, and RDL2C. This makes itpossible to make uniform the width of the resist film sandwiched betweenthe entirety of the rewiring group comprised of the rewirings RDL2A,RDL2B, and RDL2C and the dummy pattern DP2 throughout the entirety ofthe rewiring group. This means that an inverted taper degree of therewirings RDL2A, RDL2B, and RDL2C in the rewiring group can besuppressed uniformly throughout the entirety of the rewiring group. Inparticular, by making, for example the space SP2 between the rewiringRDL2A and the rewiring RDL2B in the region A3 shown in FIG. 9 equal tothe space SP1 between the rewiring group and the dummy pattern DP2, notonly the uniformity of the width of the resist film (corresponding tothe width of the space SP1) sandwiched between the entirety of therewiring group and the dummy pattern DP2 but also the uniformity of thewidth (corresponding to the width of the space SP2) of the resist filmsandwiched between the rewiring groups can be enhanced. Further, thewidth of the space SP1 between the rewiring RDL1 and the dummy patternDP1 is made equal to the width of the space SP1 between the rewiringgroup (rewirings RDL2A, RDL2B, and RDL2C) and the dummy pattern DP2.This makes it possible to enhance the uniformity of the width of theresist film sandwiched between the rewirings (RDL1, RDL2A, RDL2B, andRDL2C) and the dummy patterns (DP1 and DP2) throughout the entirety ofthe rewrings formed on the semiconductor chip. As a result, according tothe characteristic of First Embodiment, thinning of the bonding filmresulting from the inverted tapered side surface of the rewirings (RDL1,RDL2A, RDL2B, and RDL2C) formed on the semiconductor chip CHP can besuppressed throughout the rewirings (RDL1, RDL2A, RDL2B, and RDL2C).According to the characteristic of First Embodiment, therefore, peelingof the bonding film or generation of foreign matters due to film peelingcan be suppressed. The semiconductor device thus obtained can thereforehave improved reliability and it can be manufactured at an improvedyield.

<Method of Manufacturing Semiconductor Device According to FirstEmbodiment>

Next, a method of manufacturing a semiconductor device according toFirst Embodiment will be described referring to drawings. First, asemiconductor substrate (semiconductor wafer) made of, for example,silicon is provided and semiconductor elements typified by a pluralityof field effect transistors are formed on the semiconductor substrate. Amultilayer wiring layer is then formed on the semiconductor substratehaving thereon the field effect transistors. FIG. 11 shows an interlayerinsulating film IL formed on the uppermost layer of the multilayerwiring layer. As shown in FIG. 11, a conductor film made of, forexample, an aluminum film or aluminum alloy film (AlSi film, AlSiCufilm, or the like) is formed on the interlayer insulating film IL. Byusing photolithography and etching, the conductor film is patterned intoa pad PD.

A surface protection film PAS is then formed on the interlayerinsulating film IL that covers the pad PD. The surface protection filmPAS is made of, for example, a silicon oxide film or a silicon nitridefilm and it can be formed using, for example, CVD (chemical vapordeposition). As shown in FIG. 12, by using photolithography and etching,an opening portion OP1 is then formed in the surface protection filmPAS. At this time, a partial region of the pad PD is exposed from thebottom surface of the opening portion OP1.

As shown in FIG. 13, after formation of a polyimide film PIF1 havingphotosensitivity on the surface protection film PAS having therein theopening portion OP1, an opening portion OP2 is formed in the polyimidefilm PIF1 by photolithography. This opening portion OP2 couples with theopening portion OP1 formed in the surface protection film PAS.

Next, as shown in FIG. 14, a barrier conductor film BCF is formed on thepolyimide film PIF1 including the inner wall of the opening portion OP1and the inner wall of the opening portion OP2. This barrier conductorfilm BCF is made of, for example, a titanium film or a titanium nitridefilm and it can be formed, for example, by sputtering. A seed film SDFmade of a copper film is then formed on the barrier conductor film BCF,for example, by sputtering.

Then, as shown in FIG. 15, after formation of a resist film PR1 on theseed film SDF, the resist film PR1 is patterned by photolithography.Patterning of the resist film PR1 is performed so as to form an openingin a rewiring formation region. More specifically, in First Embodiment,an opening portion OP(L) for forming a wiring and an opening portionOP(D) for forming a dummy pattern are formed in the resist film PR1 asshown in FIG. 15. Since the opening portion OP(L) for forming the wiringand the opening portion OP(D) for forming the dummy pattern are placedto be close to each other, a width L of the resist film PR1 sandwichedbetween the opening portion OP(L) for forming the wiring and the openingportion OP(D) for forming the dummy pattern becomes small. Then, theresist film PR1 is cured by curing treatment through exposure of thepatterned resist film PR1 to ultraviolet rays. At this time, the surfaceof the resist film PR1 is likely to shrink, but the width L of theresist film PR1 sandwiched between the opening portion OP(L) for formingthe wiring and the opening portion OP(D) for forming the dummy patternis small so that an absolute amount of shrinkage of surface of theresist film PR1 can be reduced. As a result, according to FirstEmbodiment, the opening portion OP(L) for forming the wiring issuppressed from having a tapered side surface.

As shown in FIG. 16, by using, for example, electroplating, a copperfilm CUF that fills the opening portion OP1, the opening portion OP2,and the opening portion OP(L) for forming the wiring via the barrierconductor film BCF and is allocated over the polyimide film PIF1 isformed and at the same time, a copper film CUF that fills the openingportion OP(D) for forming the dummy pattern and is allocated over thepolyimide film PIF1 is formed. At this time, in First Embodiment, theopening portion OP(L) for forming the wiring is suppressed from having atapered side surface so that the copper film CUF with which the openingportion OP(L) for forming the wiring is filled is suppressed from havingan inverted tapered side surface.

Next, as shown in FIG. 17, the patterned resist film PR1 is removed andthen, the seed film SDF exposed by the removal of the resist film PR1 isremoved. This enables formation of the rewiring RDL1 and the dummypattern DP1 adjacent to each other. At this time, the dummy pattern DP1is comprised of a closed pattern surrounding, in plan view, the rewiringRDL1 , while having a space therebetween (Refer to FIG. 9).

In the drawings of FIG. 17 and thereafter, the copper film CUF and theseed film SDF lying below the copper film CUF will be expressed as onefilm, that is, the copper film CUF.

Next, as shown in FIG. 18, a stacked film PDF is formed on the surfaceand the side surface of the rewiring RDL1 and the surface and the sidesurface of the dummy pattern DP1, for example, by sputtering, followedby formation of a titanium film TF on this stacked film PDF. The stackedfilm PDF can be comprised of, for example, a titanium film and apalladium film on the titanium film. In First Embodiment, since therewiring RDL1 (copper film CUF) is suppressed from having an invertedtapered side surface, thinning of the stacked film PDF and the titaniumfilm TF formed on the side surface of the rewiring RDL1 can besuppressed. This means that even when sputtering having directivity isused for the formation of the stacked film PDF and the titanium film TF,the stacked film PDF and the titanium film TF formed on the side surfaceof the rewiring RPDL1 can have a thickness equal to that of these filmson the surface.

Next, as shown in FIG. 19, after formation of a resist film PR2 on thetitanium film TF, the resist film PR2 is patterned by photolithography.Patterning of the resist film PR2 is performed so as to cover each ofthe rewiring RDL1 and the dummy pattern DP1.

Then, as shown in FIG. 20, the titanium film TF exposed from the resistfilm PR2 is removed by wet etching with the patterned resist film PR2 asa mask. As shown in FIG. 21, after removal of the patterned resist filmPR2, the stacked film PDF and the barrier conductor film BCF arepatterned by wet etching with the exposed titanium film TF as a mask. Atthis time, during the step of removing the barrier conductor film BCF,the titanium film TF is removed together. In First Embodiment, since therewiring RDL1 (copper film CUF) is suppressed from having an invertedtapered side surface, the stacked film PDF and the titanium film TFformed on the side surface of the rewiring RDL1 have adequate thickness.Even wet etching is not likely to cause peeling of the stacked film PDFat the side surface of the rewiring RDL1 and therefore, corrosion of therewiring RDL1 (copper film CUF) resulting from film peeling can besuppressed. Further, since the film peeling is suppressed, generation offoreign matters is suppressed. According to First Embodiment, therefore,the semiconductor device thus obtained can have improved reliability andin addition, it can be manufactured with an improved yield.

Next, as shown in FIG. 22, a polyimide film PIF2 is formed so as tocover the rewiring RDL1 and the dummy pattern DP1. An opening portionOP3 exposing a portion of the rewiring RDL1 is then formed in thepolyimide film PIF2 by photolithography. At this time, the stacked filmPDF is exposed from the opening portion OP3. The rewiring structure ofFirst Embodiment can be formed as described above. The semiconductorwafer is then divided into individual chip regions by dicing and thus, aplurality of semiconductor chips is obtained. By performing a typicalfabrication step, manufacture of the semiconductor device of FirstEmbodiment can be completed.

Next, a technical concept relating to creation of layout datacorresponding to the layout (refer to FIG. 9) of the above-describedwiring will be described.

More specifically, a layout data creation apparatus for creating layoutdata corresponding to the layout, in plan view, including a rewiring anda dummy pattern made of a closed pattern surrounding the rewiring, whilehaving a space therebetween will be described.

<Hardware Configuration of Layout Data Creation Apparatus>

First, hardware configuration of the layout data creation apparatus inFirst Embodiment will be described. FIG. 23 shows one example of thehardware configuration of a layout data creation apparatus LDA in FirstEmbodiment. The configuration shown in FIG. 23 is only one example ofthe hardware configuration of the layout data creation apparatus LDA.The hardware configuration of the layout data creation apparatus LDA isnot limited to the configuration shown in FIG. 23 but may be anotherconfiguration.

In FIG. 23, the layout data creation apparatus LDA in First Embodimentis equipped with a CPU (central processing unit) 1 that executes aprogram. This CPU1 is electrically coupled to, for example, a ROM (readonly memory) 2, a RAM (random access memory) 3, and a hard disk device12 via a bus 13 so as to control these hardware devices.

The CPU1 is also coupled to an input device and an output device via thebus 13. Examples of the input device include a keyboard 5, a mouse 6, acommunication board 7, and a scanner 11. Examples of the output deviceinclude a display 4, a communication board 7, and a printer 10. Further,the CPU 1 may be coupled to, for example, a removable disk device 8 orCD/DVD-ROM device 9.

The layout data creation apparatus LDA may be coupled to, for example, anetwork. For example, when the layout data creation apparatus LDA iscoupled to an external apparatus via the network, the communicationboard 7 configuring a portion of the layout data creation apparatus LDAis coupled to LAN (local area network), WAN (wide area network), orinternet.

The RAM 3 is an example of volatile memories, while recording media suchas ROM 2, removable disk device 8, CD/DVD-ROM device 9, and hard diskdevice 12 are examples of nonvolatile memories. These volatile andnonvolatile memories configure a memory device of the layout datacreation apparatus LDA.

The hard disk device 12 stores therein, for example, an operating system(OS) 121, a program group 122, and a file group 123. The CPU1 executes aprogram included in the program group 122 while making use of theoperating system 121. The RAM 3 temporarily stores therein at least aportion of the program of the operating system 121 and an applicationprogram, each to be executed by the CPU1, and also stores various datanecessary for the processing by the CPU1.

The ROM 2 stores therein a BIOS (basic input output system) program andthe hard disk device 12 stores therein a boot program. When the layoutdata creation apparatus LDA is started, the BIOS program stores in theROM 2 and the boot program stores in the hard disk device 12 areexecuted and by the BIOS program and the boot program, the operatingsystem 121 is booted.

The program group 122 stores therein a program for realizing thefunction of the layout data creation apparatus LDA and this program isread and executed by the CPU1. The file group 123 stores therein, aseach file item, information, data, signal values, variables, andparameters showing the processing results by the CPU1.

The file is stored in the hard disk device 12 or recording media such asmemory. The information, data, signal values, variables, and parametersstored in the hard disk device 12 or recording media such as memory areread by the CPU1 into a main memory or a cache memory and are used forthe operation of the CPU1 typified by extraction, search, reference,comparison, arithmetic operation, processing, editing, outputting,printing, and displaying. For example, during the operation of the CPU1,the information, data, signal values, or parameters are storedtemporarily in a main memory, a register, a cache memory, or a buffermemory.

The function of the layout data creation apparatus LDA may be realizedusing firmware stored in the ROM 2 or may be realized using onlysoftware, only hardware typified by element/device/substrate/wiring,combination of software and hardware, or combination further withfirmware. The firmware and software are stored as a program in recordingmedia typified by the hard disk device 12, a removable disk, a CD-ROM,or a DVD-ROM. The program is read and executed by the CPU1. This meansthat the program makes a computer function as the layout data creationapparatus LDA.

Thus, the layout data creation apparatus LDA in First Embodiment is acomputer equipped with the CPU 1 as a processing apparatus, the harddisk device 12 as a memory device, a keyboard, mouse, or communicationboard as an input device, and a display, a printer, or a communicationboard as an output device. Each function of the layout data creationapparatus LDA is realized making use of the above-described processingdevice, memory device, input device, and output device.

<Functional Configuration of Layout Data Creation Apparatus>

Next, the functional configuration of the layout data creation apparatusLDA in First Embodiment will be described.

FIG. 24 shows a functional block configuration of the layout datacreation apparatus LDA in First Embodiment. In FIG. 24, the layout datacreation apparatus LDA in First Embodiment has an input unit IU, a firstpattern data creation unit FDU, a second pattern data creation unit SDU,a dummy pattern data creation unit DPU, a layout data creation unit LDU,and an output unit OU, and a data memory unit.

The input unit IU is configured so as to input wiring pattern datacorresponding to a wiring pattern of a plurality of wirings and thewiring pattern data input into the layout data creation apparatus LDAfrom this input unit IU is stored in the data memory unit DMU.

The first pattern data creation unit FDU is configured so as to create,based on the wiring pattern data, first pattern data corresponding to afirst pattern obtained by widening the wiring pattern by a widthcorresponding to the width of a space. The first pattern data created atthe first pattern data creation unit FDU are stored in the data memoryunit DMU.

The second pattern data creation unit SDU is configured so as to create,based on the first pattern data created at the first pattern datacreation unit FDU, second pattern data corresponding to a second patternobtained by widening the first pattern by a width corresponding to eachof the dummy patterns. The second pattern data created at the secondpattern data creation unit SDU are stored in the data memory unit DMU.

The dummy pattern data creation unit DPU is configured so as to createdummy pattern data corresponding to a plurality of dummy patterns bysubtracting the first pattern data created by the first pattern datacreation unit FDU from the second pattern data created by the secondpattern data creation unit SDU. The dummy pattern data created by thedummy pattern data creation unit DPU are stored in the data memory unitDMU.

The layout data creation unit LDU is configured so as to create layoutdata corresponding to a layout pattern including the rewiring and dummypattern by using the wiring pattern data stored in the data memory unitDMU and the dummy pattern data created by the dummy pattern datacreation unit DPU in combination. The layout data created by the layoutdata creation unit LDU are stored in the data memory unit DMU.

The output unit OU is configured so as to output the layout data createdby the layout data creation unit LDU.

<Layout Data Creation Method>

The layout data creation apparatus LDA in First Embodiment is configuredas described above. A layout data creation method using this layout datacreation apparatus LDA will next be described referring to somedrawings.

FIG. 25 is a flow chart showing the flow of the layout data creationmethod in First Embodiment. First, the layout data creation apparatusLDA inputs, from the input unit IU, wiring pattern data corresponding toa wiring pattern of a plurality of rewirings (S101). More specifically,for example, wiring pattern data corresponding to a wiring pattern WPNshown in FIG. 26 are input from the input unit IU.

Next, the first pattern data creation unit FDU of the layout datacreation apparatus LDA creates, based on the wiring pattern data inputfrom the input unit IU, first pattern data corresponding to a firstpattern obtained by widening the wiring pattern by a width of a space(S102). More specifically, the first pattern creation unit FDU creates,based on the wiring pattern data corresponding to the wiring pattern WPNshown in FIG. 26, first pattern data corresponding to the first patternFPN obtained by widening the wiring pattern by a width corresponding toa width S of a space as shown in FIG. 27. A pattern indicated by abroken line in FIG. 27 corresponds to the wiring pattern WPN shown inFIG. 26.

The second pattern data creation unit SDU of the layout data creationapparatus LDA then creates, based on the first pattern data created bythe first pattern data creation unit FDU, second pattern datacorresponding to a second pattern obtained by widening the first patternby a width of each of a plurality of dummy patterns (S103). Morespecifically, the second pattern data creation unit SDU creates, basedon the first pattern data corresponding to the first pattern FPN shownin FIG. 27, second pattern data corresponding to the second pattern SPNobtained by widening by a width W of the dummy pattern as shown in FIG.28. Also in FIG. 28, a pattern indicated by a broken line corresponds tothe wiring pattern WPN shown in FIG. 26.

The dummy pattern data creation unit DPU of the layout data creationapparatus LDA creates dummy pattern data corresponding to a plurality ofdummy patterns by subtracting the first pattern data created by thefirst pattern data creation unit FDU from the second pattern datacreated by the second pattern data creation unit SDU (S104). Morespecifically, the dummy pattern data creation unit DPU subtracts thefirst pattern data corresponding to the first pattern FPN shown in FIG.27 from the second pattern data corresponding to the second pattern SPNshown in FIG. 28. The dummy pattern DPN having a width W shown in FIG.29 is thus formed.

The layout data creation unit LDU of the layout data creation apparatusLDA creates layout data corresponding to a layout pattern including therewiring and the dummy pattern, by using, in combination, the wiringpattern data input from the input unit IU and the dummy pattern datacreated by the dummy patter data creation unit DPU (S105). Morespecifically, the layout data creation unit LDU, creates layout datacorresponding to a layout pattern LPN including the rewiring and thedummy pattern as shown in FIG. 30 by using, in combination, the wiringpattern data corresponding to the wiring pattern WPN shown in FIG. 26and the dummy pattern data corresponding to the dummy pattern DPN shownin FIG. 29.

The layout data created by the layout data creation unit LDU are thenoutput from the output unit OU (S106). As described above, the layoutdata creation method in First Embodiment is thus achieved.

<<Correction Processing>>

Further in First Embodiment, layout data are created by subjecting thelayout pattern LPN shown in FIG. 30 to correction processing in thelayout data creation unit LDU. This correction processing will next bedescribed.

First, first correction processing focused on a region A2 of FIG. 30will be described. FIGS. 31A and 31B are schematic views describing thedetails of the first correction processing in the layout data creationunit LDU. As shown in FIG. 31A, the rewiring RDL1 and the rewiring RDL2Chave therebetween the dummy pattern DP1 and the dummy pattern DP2. Inthis drawing, the minimum distance (space) allowable for the rewiring isset at 2 μm. At this time, as shown in FIG. 31A, a distance between thedummy pattern DP1 and the dummy pattern DP2 is 1 μm, which is notallowed because it is smaller than 2 μm, the minimum distance allowedfor the rewiring. In this case, the layout data creation unit LDUexecutes first correction processing for integrally coupling the dummypattern DP1 to the dummy pattern DP2 as shown in FIG. 31B. This makes itpossible to remove a space smaller than the minimum distance allowed forthe rewiring. This means that in First Embodiment, the layout datacreation unit LDU creates, when a distance between a portion of thedummy pattern DP1 and a portion of the dummy pattern DP2 is narrowerthan the predetermined distance, layout data by carrying out correctionso as to integrally couple the portion of the dummy pattern DP1 to theportion of the dummy pattern DP2. By the first correction processing,for example, the pattern shown in the region 2A of FIG. 30 is correctedinto a pattern shown in the region A2 of FIG. 9.

Next, second correction processing focused on a region A3 of FIG. 30will be described. FIGS. 32A and 32B are schematic views describing thedetails of the second correction processing in the layout data creationunit LDU. As shown in FIG. 32A, the rewiring RDL2A and the rewiringRDL2B have therebetween the dummy pattern DP1. In this drawing, theminimum width allowed for the rewiring is set at 2 μm. At this time, asshown in FIG. 32A, the width of the dummy pattern DP1 is 1 μm, which isnot allowed because it is smaller than 2 μm, the minimum width allowedfor the rewiring. In this case, the layout data creation unit LDUexecutes second correction processing for widening the width of therewiring RDL2A and the width of the rewiring RDL2B as shown in FIG. 32Bwithout providing the dummy pattern DP1. This makes it possible to omitformation of the dummy pattern DP1 having a width smaller than theminimum width allowed for the rewiring. For example, supposing thatthere is a layout in which a distance between a portion of the rewiringRDL2A and a portion of the rewiring RDL2B is wider than thepredetermined distance; and when one dummy pattern DP1 is placed betweenthe portion of the rewiring RDL2A and the portion of the rewiring RDL2B,the width of the one dummy pattern DP1 becomes smaller than thepredetermined distance. In this case, the layout data creation unit LDUcreates layout data by, instead of placing the one dummy pattern DP1,carrying out correction processing so as to widen the width of theportion of the rewiring RDL2A and the portion of the rewiring RDL2B toadjust the distance between the portion of the rewiring RDL2A and theportion of the rewiring RDL2B to the predetermined distance. By thissecond correction processing, the pattern shown in the region A3 of FIG.30 is corrected into the pattern shown in the region A3 of FIG. 9. Inshort, by the second correction processing in the layout data creationunit LDU, the width of the space SP2 shown in the region A3 of FIG. 9 isadjusted to be roughly equal to that of the space SP1. In such a manner,the layout pattern including the rewirings (RDL1, RDL2A, RDL2B, andRDL2C) and the dummy patterns (DP1 and DP2) shown in FIG. 9 is finallyactualized.

<Layout Data Creation Program>

The layout data creation method executed in the above-described layoutdata creation apparatus LDA can be achieved according to a layout datacreation program that allows a computer to perform layout data creationprocessing. For example, a layout data creation program of FirstEmbodiment can be introduced into the layout data creation apparatus LDAcomprised of a computer as shown in FIG. 23 as one of the program group122 stored in the hard disk device 12. The layout data creation methodin First Embodiment can be achieved by allowing the computer of thelayout data creation apparatus LDA to carry out this layout datacreation program.

The layout data creation program for allowing a computer to carry outeach processing for creating layout data can be recorded in a recordingmedium readable by a computer and delivered. Examples of such arecording medium include magnetic recording media such as hard disk andflexible disk, optical recording media such as CD-ROM and DVD-ROM, andhardware devices typified by a nonvolatile memory such as ROM andEEPROM.

Second Embodiment

FIG. 33 shows a planar layout configuration of a semiconductor chip CHPin Second Embodiment. As shown in FIG. 33, the semiconductor chip CHP ofSecond Embodiment has an occupancy control pattern OCP in the same layeras the rewirings (RDL1, RDL2A, RDL2B, and RDL2C) and the dummy patterns(DP1 and DP2). This means that in Second Embodiment, the polyimide filmPIF1 shown in FIG. 10 has thereon the occupancy control pattern OCP.According to Second Embodiment, the occupancy of copper films (copperfilms configuring the rewiring, the dummy pattern, and the occupancycontrol pattern, respectively) on the surface of the semiconductor chipCHP can be controlled by it. The copper films on the surface of thesemiconductor chip CHP are formed, for example, using electroplating.When the occupancy of the copper film is very small, the copper filmscannot be formed stably by electroplating. There may occur the casewhere even if the areas of the copper films configuring, for example,the rewirings (RDL1, RDL2A, RDL2B, and RDL2C) and the dummy patterns(DP1 and DP2) are totalized, an occupancy enough for stably formingthese copper films by electroplating cannot be secured. In this case, byproviding the semiconductor chip CHP with the occupancy control patternOCP as in Second Embodiment, the occupancy of copper films can beimproved to enable stable formation of them by electroplating. As aresult, according to Second Embodiment, the respective copper filmsconfiguring the rewirings (RDL1, RDL2A, RDL2B, and RDL2C), the dummypatterns (DP1 and DP2), and the occupancy control pattern OCP can beformed stably. Due to a marked increase in the occupancy of copperfilms, however, warp of the semiconductor substrate appears as a problemso that attention should be paid to this point. For example, theoccupancy of copper films is desirably from about 35% to 60% both fromthe standpoint of stably forming copper films by electroplating and fromthe standpoint of suppressing generation of warp of a semiconductorwafer.

FIG. 33 shows an occupancy control pattern OCP having an octagonalplanar shape. The planar shape is not limited to it and the occupancy ofcopper films can be controlled even when it has a rectangular (square),triangular, hexagonal, circular, or cross shape.

Third Embodiment

FIG. 34 shows the planar layout configuration of a semiconductor chipCHP in Third Embodiment. As shown in FIG. 34, the semiconductor chip CHPof Third Embodiment has a dummy pattern DP3 so as to surround, in planview, the dummy pattern DP1 and the dummy pattern DP2. The dummy patternDP3 is comprised of a closed pattern surrounding the dummy pattern DP1and the dummy pattern DP2, while having a space therebetween.

According to Third Embodiment, the rewirings (RDL1, RDL2A, RDL2B, andRDL2C) can be suppressed from having an inverted tapered side surfaceand at the same time, the dummy pattern DP1 and the dummy pattern DP2can be suppressed from having an inverted tapered side surface. In FirstEmbodiment, the dummy pattern DP1 and the dummy pattern DP2 can suppressthe rewirings (RDL1, RDL2A, RDL2B, and RDL2C) from having an invertedtapered side surface and are therefore effective for preventingcorrosion of the copper film configuring the rewiring. In FirstEmbodiment, on the other hand, for example, as shown in FIG. 10, thedummy pattern DP1 is likely to have an inverted tapered side surface.This means that a generation potential of foreign matters resulting fromfilm peeling from the side surface of the dummy pattern DP1 cannot besuppressed completely. According to Third Embodiment, on the other hand,the dummy pattern DP3 surrounds the dummy pattern DP1 and the dummypattern DP2, while having a space therebetween. According to ThirdEmbodiment, therefore, the dummy pattern DP1 and the dummy pattern DP2can each be suppressed from having an inverted tapered side surface,leading to reduction in generation potential of foreign mattersresulting from film peeling.

Further, according to Third Embodiment, the semiconductor chip has, inaddition to the dummy pattern DP1 and the dummy pattern DP2, the dummypattern DP3. Due to the dummy pattern DP3 thus provided, the occupancyof copper films can be improved. According to Third Embodiment, as aresult, copper films can be formed stably by electroplating. In the casewhere an occupancy enough for stably forming copper films byelectroplating cannot be secured, for example, as shown in FIG. 35, anoccupancy control pattern OCP may be provided on the surface of thesemiconductor chip CHP.

MODIFICATION EXAMPLE

FIG. 36 shows a planar layout configuration of a semiconductor chip CHPin Modification Example. As shown in FIG. 36, the semiconductor chip CHPof Modification Example has, in plan view, a dummy pattern DP3 thatsurrounds the dummy pattern DP1 and the dummy pattern DP2 and furtherhas a dummy pattern DP4 outside the dummy pattern DP3. According toModification Example, the rewirings (RDL1, RDL2A, RDL2B, and RDL2C) canbe suppressed from having an inverted tapered side surface and moreover,the dummy patterns (DP1, DP2, and DP3) can be suppressed from having aninverted tapered side surface. Further, the occupancy of copper filmscan be improved by providing not only the dummy pattern DP3 but also thedummy pattern DP4. As a result, Modification Example further facilitatesstable formation of copper films by electroplating.

As shown in FIG. 36, when the dummy pattern DP4 is comprised of a closedpattern surrounding the dummy pattern DP3, while having a spacetherebetween and a portion of the dummy pattern DP4 protrudes from thesemiconductor chip CHP, removal of the protruding portion is required.

The invention made by the present inventors has been describedspecifically based on some embodiments. Needless to say that theinvention is however not limited to or by these embodiments but can bechanged in various ways without departing from the gist of theinvention.

The above-described embodiment includes the following modes.

(Appendix 1)

A layout data creation apparatus for creating layout data correspondingto a layout pattern including a wiring pattern corresponding to aplurality of wirings, a first conductor pattern, among a plurality ofconductor patterns comprised of a closed pattern surrounding some of theplurality of wirings, while having a space therebetween, and a secondconductor pattern, among the plurality of conductor patterns comprisedof a closed pattern surrounding some of the other ones of the pluralityof wirings, while having a space therebetween, including;

an input unit for inputting wiring pattern data corresponding to thewiring pattern;

a memory unit for storing the wiring pattern data therein;

a first pattern data creation unit for creating, based on the wiringpattern data, first pattern data corresponding to a first patternobtained by widening the wiring pattern by the width of the space;

a second pattern data creation unit for creating, based on the firstpattern data, second pattern data corresponding to a second patternobtained by widening the first pattern by the width of each of theconductor patterns,

a conductor pattern data creation unit for creating conductor patterndata corresponding to the conductor patterns by subtracting the firstpattern data from the second pattern data;

a layout data creation unit for creating the layout data correspondingto the layout pattern by using the wiring pattern data and the conductorpattern data in combination; and

an output unit for outputting the layout data.

(Appendix 2)

The layout data creation apparatus as described above in Appendix 1,wherein:

the layout data creation unit creates, when a distance between a portionof the first conductor pattern and a portion of the second conductorpattern is narrower than a predetermined distance, the layout data bymaking a correction to integrally couple the portion of the firstconductor pattern to the portion of the second conductor pattern.

(Appendix 3)

The layout data creation apparatus as described above in Appendix 1,

wherein the layout data creation unit creates the layout data by makinga correction, when in a first wiring and a second wiring, among theplurality of wirings, a distance between a portion of the first wiringand a portion of the second wiring is wider than a predetermineddistance while when one of the plurality of conductor patterns is placedbetween the portion of the first wiring and the portion of the secondwiring and it has a width narrower than the predetermined distance,instead of placing one of the conductor patterns, to widen the width ofthe portion of the first wiring and the width of the portion of thesecond wiring to adjust a distance between the portion of the firstwiring and the portion of the second wiring to the predetermineddistance.

(Appendix 4)

A layout data creation method for creating, using a computer, layoutdata corresponding to a layout pattern including, in plan view, a wiringpattern corresponding to a plurality of wirings, a first conductorpattern, among a plurality of conductor patterns comprised of a closedpattern surrounding some of the plurality of wirings, while having aspace therebetween, and a second conductor pattern, among the pluralityof conductor patterns comprised of a closed pattern surrounding some ofthe other ones of the plurality of wirings, while having a spacetherebetween, including the steps of:

(a) allowing the computer to input wiring pattern data corresponding tothe wiring pattern;

(b) allowing the computer to store the wiring pattern data;

(c) allowing the computer to create, based on the wiring pattern data,first pattern data corresponding to a first pattern obtained by wideningthe wiring pattern by the width of the space;

(d) allowing the computer to create, based on the first pattern data,second pattern data corresponding to a second pattern obtained bywidening the first pattern by the width of each of the plurality ofconductor patterns;

(e) allowing the computer to create conductor pattern data correspondingto the plurality of conductor patterns by subtracting the first patterndata from the second pattern data;

(f) allowing the computer to create the layout data corresponding to thelayout pattern by using the wiring pattern data and the conductorpattern data in combination; and

(g) allowing the computer to output the layout data.

(Appendix 5)

A layout data creation program that allows a computer to create layoutdata corresponding to a layout pattern including, in plan view, a wiringpattern corresponding to a plurality of wirings, a first conductorpattern, among a plurality of conductor patterns comprised of a closedpattern surrounding some of the plurality of wirings, while having aspace therebetween, and a second conductor pattern, among the pluralityof conductor patterns comprised of a closed pattern surrounding some ofthe other ones of the plurality of wirings, while having a spacetherebetween, and allows the computer to execute:

(a) processing for inputting wiring pattern data corresponding to thewiring pattern,

(b) processing for storing the wiring pattern data;

(c) processing, based on the wiring pattern data, for creating firstpattern data corresponding to a first pattern obtained by widening thewiring pattern by the width of the space;

(d) processing, based on the first pattern data, for creating secondpattern data corresponding to a second pattern obtained by widening thefirst pattern by the width of each of the plurality of conductorpatterns;

(e) processing for creating conductor pattern data corresponding to theplurality of conductor patterns by subtracting the first pattern datafrom the second pattern data;

(f) processing for creating the layout data corresponding to the layoutpattern by using the wiring pattern data and the conductor pattern datain combination; and

(g) processing for outputting the layout data.

(Appendix 6)

A computer-readable recording medium having, recorded therein, thelayout data creation program as described above in Appendix 5.

What is claimed is:
 1. A semiconductor device, comprising a first polyimide film; a wiring formed over the first polyimide film; a conductor pattern formed over the first polyimide film; a second polyimide film that covers the wiring and the conductor pattern; and an opening portion that exposes a portion of the wiring in the second polyimide film, wherein, in plan view, the conductor pattern is comprised of a closed pattern surrounding the wiring, while having a space therebetween. 